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NJU26060 Series
NJU26060 Series Hardware Specification
General Description
The NJU26060 Series is a high performance 24-bit digital signal processor. The NJU26060 Series provides stereo PWM modulators, one Sampling Rate Convertor(SRC), Digital Interface Transemitor(DIT) and four GPI/O ports. The NJU26060 Series with the OTP(One Time Programmable) function provides the wide range of applications of sound technologies and fast time to market service.
Package
NJU26060V
Features
- Hardware * 24bit Fixed-point Digital Signal Processing * Maximum Clock Frequency : 24.576MHz (Standard), Embedded PLL Circuit * PWM modulator : stereo 4ch Outputs * Sampling rate converter (SRC) : Fs=8kHz 192kHz 48kHz * Digital interface transmitter (DIT) * Digital Audio Interface : 3 Input ports / 3 Output ports * Digital Audio Format : I2S 24bit, Left-justified, Right-justified, BCK : 32/64fs * Master / Slave Mode - Sampling Rate Converter: Slave mode - In Master Mode: MCKO(256 or 512fs ), BCKO(64 or 32fs ), BCK (1fs ) * Host Interface - I2C Bus ( Fast-mode/400kbps) * Power Supply : VDD = 3.3V * Input terminal: : 5V Input tolerant * Package : SSOP44 (Pb-Free)
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NJU26060 Series
DSP Block Diagram
24Bit Fixed-point DSP Core BCKO LRO SDI0 SDI1 SDI2 Serial Audio Interface (Master) Over Sampling Digital Filter Over Sampling Digital Filter
PWM Modulator 0 Delta-Sigma Modulator Delta-Sigma Modulator PWM Generator PWM Generator OUTLP0 OUTLN0 OUTRP0 OUTRN0 PWMEN0
SDI Select
PWM_MUTEb PWM_DISb PWM_ERRb
BCKO LRO 512fs BCKI LRI SCL I2C INTERFACE SDA
Sampling Rate Convertor (Slave)
PROGRAM CONTROL 24Bit x 24Bit MULTIPLIER ALU
PWM Modulator 1 Over Sampling Digital Filter Delta-Sigma Modulator PWM Generator SDO0 Over Sampling Digital Filter Delta-Sigma Modulator PWM Generator SDO1 PWMEN1 OUTRP1 OUTRN1 OUTLP1 OUTLN1
ADDRESS GENERATION UNIT
RESETb BCKO LRO MCKO CLKOUT CLK TIMING GENERATOR / PLL 2048fs 256fs 512fs
S/PDIF Transmitter SDO
GPIO INTERFACE
GPIO[1] GPIO[3][2][0]
1.8V FIRMWARE OTP PROGRAM RAM DATA RAM0 DATA RAM1
LDO
VREGO
Fig.1 NJU26060 Series Block Diagram
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NJU26060 Series
Pin Configuration
RESETb PWM_MUTE PWM_DISb SDA SCL LRI BCKI SDI0 TEST TEST REGDISb VDD VSS VREGO VDDPLL VSSPLL PWMEN1 OUTRN1 OUTRP1 OUTLN1 OUTLP1 VSSPWM
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
44 43 42 41 40 39 38 37 36 35
BCKO LRO MCKO SDO GPIO0 GPIO1 GPIO2 GPIO3 TEST CLK CLKOUT VDD VSS VREGO TEST PWM_ERRb PWMEN0 OUTRN0 OUTRP0 OUTLN0 OUTLP0 VDDPWM
NJU26060-xxx SSOP44
34 33 32 31 30 29 28 27 26 25 24 23
Fig.2 NJU26060 Series Pin Configuration
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NJU26060 Series
Pin Description
Table 1.
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
Pin Description
Symbol RESETb PWM_MUTEb PWM_DISb SDA SCL LRI BCKI SDI0 TEST TEST REGDISb VDD VSS VREGO VDDPLL VSSPLL PWMEN1 OUTRN1 OUTRP1 OUTLN1 OUTLP1 VSSPWM VDDPWM OUTLP0 OUTLN0 OUTRP0 OUTRN0 PWMEN0 PWM_ERRb TEST VREGO VSS VDD CLKOUT CLK TEST GPIO3 GPIO2 GPIO1 GPIO0 SDO MCK LRO BCKO I/O I I+ I+ OD I III I I I PI O OP OP OP OP OP OP OP OP O I+ I PI O I II/O I/O I/O I/O O O O O Description Reset (RESETb="Low" : DSP Reset) PWM Block Mute request input PWM Block Standby request input I2C I/O I2C clock LR Clock Input for Fs conversion side Bit Clock Input for Fs conversion side Audio Data Input 0 (L/R) For Test (connected to VSS) For Test (connected to VSS) Built-in Power Supply Enable Power Supply +3.3V GND Built-in Power Supply Bypass PLL Power Supply +1.8V PLL Power Supply GND PWM1 enable output (PWMEN1='1': enable) PWM1 R- output / Audio Data output 1 (setting Firmware) PWM1 R+ output PWM1 L- output / Audio Data output 0 (setting Firmware) PWM1 L+ output PWM Power Supply GND PWM Power Supply +3.3V PWM0 L+ output PWM0 L- output PWM0 R+ output PWM0 R- output PWM0 enable output (PWMEN0='1': enable) PWM block stop request input (PWM_ERRb='0': PWM stop) for Test (connected to VSS) Built-in Power Supply Bypass GND Power Supply +3.3V OSC Output OSC Clock Input for Test (connected to VSS) General Purpose IO 3 / for TEST General Purpose IO 2 / for TEST General Purpose IO 1 / for TEST General Purpose IO 0 / for TEST DIT output / Audio Data Output 2 (setting Firmware) Master Clock Output for A/D, D/A LR clock Output Bit clock Output
Note :
I I+ OD I/O OP
: Input O: Output : Input (Pull-up) I -: Input (Pull-down) : Bi-directional (Open Drain) This pin requires a pull-up resistance. : Bi-directional PI: Built-in Power Supply Bypass : PWM output(supply for VDDPWM)
NOTICE: Does not keep the terminal without the pull-up resistance or the pull-down resistance open. The functions of SDIO0 to SDIO2, SDO, OUTxxx depend on the IC specifications.
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Absolute Maximum Ratings
Table2 Absolute Maximum Ratings Parameter Symbol
VDD, VDDPWM VREGO VDDPLL In I/O, O/D Terminal Voltage * Out CLK CLKOUT Power Dissipation Operating Temperature Storage Temperature * VDD * VDDPW * VREGO * VDDPLL * Vx(IN) * Vx(OD) * Vx(I/O) * Vx(OUT) * Vx(CLK) * Vx(CLKOUT) : 12, 33 pin : 23 pin : 14, 31 pin : 15 pin : 1~3, 5~11, 29, 30, 36 pin : 4 pin : 37~40 pin : 17~21, 24~28, 41~44 pin : 35 pin : 34 pin Vx(IN) Vx(I/O), Vx(OD) Vx(OUT) Vx(CLK) Vx(CLKOUT) PD TOPR TSTR
( VSS=VSSPLL=VSSIO=0V, Ta=25C ) Rating Units
-0.3 to 4.2 -0.3 to 2.3 -0.3 to 2.3 -0.3 to 5.5 (VDDIO3.0V) -0.3 to 4.2 (VDDIO<3.0V) -0.3 to 4.2 -0.3 to 4.2 -0.3 to 4.2 800
It mounts on the board of the EIAJ spec. 76.2 x 114.3 x 1.6mm, 2layer, FR-4
Supply Voltage * Supply Voltage Bypass * Supply Voltage PLL *
V
V
mW C C
-40 to 85 -40 to 125
Equivalent Circuits
RPU PAD RPD VDD VREGO
CLK CLKOUT
VDD VREGO
VSS
Input Pin, I/O Pin (Input port) CLK/CLKOUT Pin
VSS
VDD or VDDPWM PAD
Output
PAD
VDD
VSS or VSSPWM
VSSIO Output Pin, I/O Pin (Output port) (4pin Open-Drain Out)
VSS
REGDISb Pin
Fig.3 NJU26060 Series Equivalent Circuits
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NJU26060 Series
Electric Characteristics
Table3 Electric Characteristics
Parameter Operating Voltage *1 Operating Current High Level Input Voltage Low Level Input Voltage High Level Output Voltage *3 Low Level Output Voltage Symbol VDD IDD VIH VIL VOH VOL IIN Terminal Leakage Current *4 IIN(PU) IIN(PD) Clock Frequency fOSC CLK Pin *5 VIN = VSS ~ VDD IOH = -1mA IOL = 1mA
( VDD=VDDPWM=3.3V, fOSC=24.576MHz, Ta=25C )
Test Condition VDD, VDDPWM Pin AT no Load, VDD + VDDPWM Min. 3.0 VDD x 0.7 0 VDD x 0.8 0 -10 -120 -10 20 45 Typ. 3.3 35 22.5792 24.576 50 Max. 3.6 50 VDD *2 VDD x 0.3 VDD VDD x 0.2 10 10 120 25 55 MHz % A V Units V mA
Ext. System Clock Duty Cycle rEC
*1 Please use the VDD ,VDDpwm within the electric characteristics. VDD ,VDDpwm is monotonous increase. Don't drop voltage under the electric characteristics after booting VDD ,VDDpwm to regulation voltage. When it turns off DSP and turns on DSP again, it is necessary to drop VDD to GND level. Then it turns on DSP again. *2 Input pin, Output pin and Open-Drain input/output pin are +5.0V tolerant except CLK input pin. *3 Except 4pin (Open-Drain I/O) input pin. *4 I IN(PU) : 2,3,29,37,38pin, I IN(PD) : 6~10,36,39,40 pin *5 Please give usually the clock of 24.576MHz using for 48kHz and 22.5792MHz using for 44.1kHz. An internal sampling frequency is 1/512 of the input clock frequency.
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1. Power ,Clock and Reset
1.1 Power Supply
The NJU26060 Series has three power supplies VDD/VSS, VDDPLL/VSSPLL and VDDPWM/VSSPWM. VDD/VSS is used as an internal core supply, VDDPLL/VSSPLL is used as an internal PLL power supply and VDDPWM/VSSPWM is used as PWM output power supply. The NJU26060 has a power supply VDD/VSS, VDDPLL/VSSPLL. To setup good power supply condition, the decoupling capacitors should be implemented at the all power supply terminals. Please use the VDD/VDDPWM within the electric characteristics. VDD/VDDPWM is monotonous increase. Don't drop voltage under the electric characteristics after booting VDD/VDDPWM to regulation voltage. When it turns off DSP and turns on DSP again, it is necessary to drop VDD/VDDPWM to GND level. Then it turns on DSP again. VDDPWM/VSSPWM is used as PWM output :OUTLP0, OUTLN0, OUTRP0, OUTLP1, OUTLN1, OUTRP1power supply. VDD/VSS has a same power supply. The NJU26060 include a built-in power supply (LDO) for internal logic. A built-in power supply generates 1.8V (-10% to +10%). VREGO (No.14,31) pin is a built-in power supply bypass pin. Connect low-ESR capacitor of 0.01uF in parallel between VSS (No.13,32) pin. The NJU26060 include PLL for internal logic and PWM modulator. PLL power has VDDPWM/VSSPWM, but an include circuit unconnected straight for each other power. PLL power is supply for VREGO (No.14). Connect the decoupling capacitor of 0.01uF in parallel between VDDPLL and VSSPLL. VSSPLL is connected VSS.
+3.3V
+ 10uF
NJU26060
11 12
0.1uF 10uF 0.01uF 0.01uF
REGDISb VDD VSS VREGO VDDPLL VSSPLL VSSPWM
10
VDD VSS VREGO
33 32 31
0.01uF 0.01uF 0.1uF 10uF
13 14 15
0.01uF
16
22
VDDPWM
23
0.01uF 10uF
Fig.4 Simple power filter sample A built-in power supply is used only for NJU26060 operation. Be not short-circuited of this pin. Do not take out the current, and connect other power supplies.
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NJU26060 Series
1.2 Input/Output terminal
It restricts, when the input terminals, the input/output terminals and the bi-directional Open-drain terminal of NJU26060, and VDD are supplied on regular voltage (VDD=3.3V), and it becomes +5V Input tolerant.
1.3 Clock
The NJU26060 CLK pin requires the system clock that should be related to the sample frequency 512 Fs using the PWM modulator. It is possible to be generated the system clock by connecting a crystal oscillator between CLK and CLKOUT. CLK/CLKOUT pins are not 5V tolerant, so check the voltage level of these pins.
Note: When the crystal oscillator supplies the clock, the characteristic of the NJU26060 series is secured. However, when the clock of external generation is supplied, the characteristic of the sampling rate converter and the PWM modulator might be depraved. 1.4 Reset
To initialize the NJU26060, RESETb pin should be set Low level during some period. After some period of Low level, RESETb pin should be High level. This procedure starts the initialization of the NJU26060. After the power supply and the oscillation of the NJU26060 becomes stable, RESETb pin must be kept Low-level more than tRESETb period. (Fig.5) After RESETb pin level goes to "High" (after reset release), a setup of the internal hardware of a Serial Host Interface completes NJU26060. Then, it will be in the state which can communicate.
Fig. 5 Reset Timing
VDD ,VDDPWM
tVREGO
3.3V(10%) 1.8V
VREGO
CLK Internal
Oscillation instability
Oscillation stability
Trigger operation
Lock-up tRESETb
RESETb
Set up a Host Interface within 1ms.
Table 4 Symbol tVREGO tRESETb
Reset time Time 10msec 10msec
NOTICE: All the output terminals are irregular from turning on the power supply to the internal reset completion. Especially, when the terminal PWMEN0/1 is used by the control signal, the redundant design is needed to protect the system. Do not stop providing clock during operation. If stopped, the built-in PLL cannot provide a normal clock toward internal NJU26060 series doesn't work correctly.
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NJU26060 Series
2. Digital Audio Clock
Digital audio data needs to synchronize and transmit between digital audio systems. When the sampling rate converter is not used, the NJU26060 series is used as a master mode. Sampling rate converter is supported for slave mode only. - In Master mode; The clock of MCKO, BCKO, and LRO is used for digital audio data transfer as a clock of other slave devices. - In Slave mode; BCKI and LRI input the clock from other maste devices.
2.1 Audio Clock Three kinds of clocks are needed for digital audio data transfer. (1) LR clock (LRI, LRO) is needed by serial-data transmission. It is the same as the sampling frequency of a digital audio signal. (2) Bit clock (BCKI, BCKO) is needed by serial-data transmission. It becomes the multiple of LR clock. (3) Master clock (MCKO) needed by A/D, D/A converter, etc. It becomes the multiple of LR clock. It is not related to serial audio data transmission. The NJU26060 series support serial data format that includes 32(32fs) or 64(64fs) BCK clocks.
The NJU26060 Series supplies the clock necessary for digital audio data transmission to an external device as a master device by each terminal of MCKO, BCKO, and LRO. On the other hand, the sampling rate converter that works as a slave device takes digital audio data with the clock input to BCKI and the terminal LRI, and converts the sampling frequency into the clock system composed of MCKO/BCKO/LRO. After internal reset ends as a master clock, the terminal MCKO sets the buffer output or 2 dividing frequency the output of the input clock to the terminal CLK. The stop is also possible according to the command of the firmware. The NJU26060 Series is used by 512 times the internal operation sampling frequency (It is 24.576MHz in the sampling frequency 48kHz). In that case, NJU26060 can output 64 times, 32 times the bit clock to of the LR clock one time the sampling frequency and of each, and 512 times and 256 times the master clock as a mastering device. Table 5 shows the relation of each clock.
Supply Clock for CLK pin Frequency and BCKO,LRO,MCKO Clock Frequency Clock Signal Multiple Frequency
LRO BCKO(32Fs) BCKO(64Fs)* MCKO(256Fs)* MCKO(512Fs) 1Fs 32Fs 64Fs 256Fs 512Fs 22.5792MHz 44.1kHz 1.4112MHz 2.8224MHz
Table
24.576MHz 48kHz 1.536MHz 3.072MHz 12.288MHz
11.2896MHz 22.5792MHz
24.576MHz * default for starting up
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NJU26060 Series
3. Sampling Rate Converter (SRC)
The NJU26060 Series provide the stereo (two channels) Sampling Rate Converter (SRC). The internal audio sampling frequency (Fs) is 1/512 of the CLK pin. The SRC can convert an arbitrary sampling frequency (Fs=8kHz to 192kHz) into the internal sampling frequency (Fs=CLK/512). For example, CLK=24.576MHz at Fs=48kHz, CLK=22.5792MHz at Fs=44.1kHz.
3.1
Automatic Sample-frequency Detection
The NJU26060 Series provide the automatic sampling-frequency detection to provide the best converting performance. When the sample frequency changes on a large scale, this automatic detection resets the SRC. To detect the sampling frequency change, the NJU26060 Series count the length of the LRI clock, every 2,048 LRI clock. In case of CLK=24.576MHz and LRI=48kHz, the count of length is 24,576/48=512. The LRI and CLK are asynchronous, so the negligible error count is about 1 clock. The detection block compares the previous counts fLRI with the current counts fLRI'. When the detection block finds that the count difference exceeds 4, the detection block resets the SRC. The detection function operates when the next condition occurs. fLRI' < 1 / {(4+CLK/ fLRI) / CLK} or fLRI' > 1 / {(4-CLK/ fLRI) / CLK}
LRI Toggle 2048 times
[Hz]
Sampling Frequency:fLRI'
Samping Rate 1 Samping Rate 2
Sampling Frequency:fLRI
Fig.6 Relation between fLRI'and fLRI'
The automatic detection can detect the frequency change as follows: In case of CLK=24.576MHz and fLRI=8kHz, the next two fLRI' frequency ranges can be detected. fLRI' < 7.989kHz or fLRI' > 8,010kHz * 2,048sample=2,048/8,000=256msec, fLRI=1/{(424.576M/8k)/24.576M} In case of CLK=24.576MHz and fLRI=192kHz, the next two fLRI' frequency ranges can be detected. fLRI' < 186.18kHz or fLRI' > 198.19kHz * 2,048sample=2,048/192,000=10.7msec, fLRI=1/{(424.576M/192k)/24.576M} The firmware can check if the SRC is reset by the automatic detection. The reset period is fixed at 2,048 X 512(1/CLK) seconds. This function is also effective in the reset period. During the reset this detection happens, the reset period becomes longer. This function is active in default. When the changing speed of the LRI clock is too slow, the automatic detection could not be detected. When the input audio signal does not meet the above frequency detection requirement with bad-quality LRI and BCKI, the SRC does not convert correctly. In this case, reset the SRC by the firmware. Also reset the SRC by the firmware once when the system powers on. The detection block cannot detect the complete stopped LRI clock. In case of the stopped LRI clock, the SRC generates the noise depending on the input signal condition. When this kind of noise happens, reset or stop the SRC function by the firmware.
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NJU26060 Series
3.2 Sampling Frequency Conversion Ratio and Group Delay
After the automatic detection reset or the firmware reset is done, the SRC generates an effective conversion output within 256 input samples. The NJU26060 Series does not generate digital noise after this kind of reset. The conversion ratio comes to the target specification and fixes conversion ratio within 16,384 input samples after the reset. After the automatic detection reset or the firmware reset, the LRI clock should be stable. In case of the sampling converter ratio is fixed, the group delay is 256 sampling frequency clocks. To transfer the data to the firmware, it takes five more sampling frequency clocks. The zero data is inputted into the SRC during the group delay period, the output data of the SRC becomes zero.
3.3 Jitter-Tolerated Dose
The SRC can accept the jitter of 0.1UI. The UI is abbreviation of unit interval. The 1UI is one LRI clock time. The UI is defined by single peak. Ex.1) Fs=8kHz Ex.2) Fs=192kHz 0.1UI = 0.1/8,000=12.5sec 0.1UI = 0.1/192,000=521nsec
The jitter-tolerated dose is shown in fig.7. The dotted line (0.1UI) is acceptable limitation to keep the performance of the SRC. The lack of data occurs above the solid line. Above the solid line, audible noise is generated. This characteristic is measured with the sine wave jitter. Also the SRC can convert the square wave with the jitter very well as far as lower than 0.1U area. Some kind of product generates high peak jitter instantaneously. For example, some kind of USB audio product. When the signal with more than 0.1U jitter is connected to the SRC, the SRC has possibility to generate audible noise.
10
1 Ampiltude [UI]
Area where data is missed and noise is generated
Deteriorates area
0.1
Excellent characteristic area
0.01 1 10 100 Jitter Frequency [Hz] 1000 10000
Fig.7 Jitter Tolerated dose
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NJU26060 Series
3.4 Sampling Rate Converter Characteristics
This section describes Sampling Rate Converter characteristics. The characteristics are measured through the serial audio I/O interface. The characteristics depend on the PWM modulator when the output is via the PWM modulator.
Table 6
Sampling rate converter: THD+N Characteristics
Input Fs(kHz) 8.0 11.025 12.0 22.05 24.0 32.0 44.1 48.0 64.0 88.2 96.0 128.0 176.0 192.0 CLK pin Frequency 22.5792MHz 24.576MHz (Inside (Inside FSO=48.0kHz) FSO=44.1kHz) -114 -120 -122 -122 -126 -125 -130 -130 -128 -128 -124 -130 -119 -125 -133 -119 -131 -134 -132 -124 -126 -130 -131 -132 -133 -134 -133 -135 dB
Parameter
Units
THD+N Frequency: 22~FSO/2(Hz) Input: 1kHz, 0dBFS Input bit Width:24bit
Table7
Sampling rate converter: Dynamic range Characteristics
Parameter
Input Fs(kHz) 8.0 11.025 12.0 22.05 24.0 32.0 44.1 48.0 64.0 88.2 96.0 128.0 176.0 192.0 CLK pin Frequency 24.576MHz 22.5792MHz (Inside (Inside FSO=48.0kHz) FSO=44.1kHz) 132 132 132 133 133 133 133 134 135 136 136 138 139 139 132 132 132 133 133 133 133 134 134 136 136 137 138 139 dB
Units
Dynamic range Frequency: 22~FSO/2(Hz) INPUT: 1kHz, -60dBFS Input bit Width 24bit A-Weight Filter
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4. Digital Audio Interface
4.1 Digital Audio Data Format
The NJU26060 Series can use three kinds of formats hereafter as industry-standard digital audio data format. (1) I2S : MSB is put on the 2nd bit of LR clock change rate.(1 bit is delayed to left stuffing) (2) Left-justified : LR clock -- MSB is placed for changing. (3) Right-justified : LSB is placed just before LR clock change rate. The main differences among three kinds of formats are in the position relation between LR clock (LRI, LRO) and an audio data (SDI, SDO). - In every format: : a left channel is transmitted previously. - In Right/Left-justified : LR clock ='High' shows a left channel. : LR clock="Low" shows a left channel. - I2S - The Bit clock BCK (BCKI, BCKO) is used as a shift clock of transmission data. The number of clocks more than the number of sum total transmission bits of a L/R channel is needed at least. - One cycle of LR clock is one sample of a stereo audio data. The frequency of LR clock becomes equal to a sample rate (fs).
4.2 Serial Audio Data Input/output
The NJU26060 Series audio interface includes 3 data input lines: SDI0, SDI1 and SDI2 (Table 8). 3 data output lines: SDO0, SDO1 and SDO2 (Table 9). Refer to each datasheet.
Table 8 Serial Audio Input Pin Description Pin No. Symbol Description 8 SDI0 Audio Data Input 0 9 SDI1 Audio Data Input 1 10 SDI2 Audio Data Input 2 Table 9 Serial Audio Output Pin Description Pin No. Symbol Description 20 OUTLN1 Audio Data Output 0 18 OUTRN1 Audio Data Output 1 41 SDO Audio Data Output 2 The serial audio output pin switches the PWM output and the DIT output by the firmware (Table1).
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The NJU26060 Series can input and output digital audio data by the following general serial audio interfaces. The default resetting it is set to I2S 64Fs 24bit. The setting can be changed according to the firmware. The NJU26060 Series operates as a mastering device that synchronizes with the clock that consists of MCKO, BCKO, and LRO (Refer to Chapter 2) SDO set to the serial audio interface, OUTRN1, and OUTLN1 are output synchronizing with these clocks. The SDI pin that has been selected with the sampling rate converter can be operated by an independent format by the input of the data of the clock of BCKI and LRI. The NJU26060 Series can use three kinds of formats hereafter as industry-standard digital audio data format; (1) I2S (2) Left-justified (3) Right-justified and 16 / 24bits data length. (Fig.8-1 to Fig8-6) An audio interface input and output data format become the same data format.
LRI, LRO BCKI, BCKO
M SB LSB 32 Clocks M SB 32 Clocks LSB Left Channel Right Channel
SDI, SDO
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Fig8-1 I S Data Format 64Fs, 24bit Data
LRI, LRO BCKI, BCKO
M SB LSB 32 Clocks M SB 32 Clocks LSB
23
2
Left Channel
Right Channel
SDI, SDO
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Fig.8-2 Left-Justified Data Format 64Fs, 24bit Data
LRI, LRO BCKI, BCKO
M SB LSB 32 Clocks M SB 32 Clocks LSB Left Channel Right Channel
SDI, SDO 2 1 0
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Fig.8-3 Right-Justified Data Format 64Fs, 24bit Data
LRI, LRO BCKI, BCKO
M SB LSB M SB 16 Clocks 16 Clocks LSB Left Channel Right Channel
SDI, SDO
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Fig.8-4
LRI, LRO BCKI, BCKO
M SB
I S Data Format 32Fs, 16bit Data
Left Channel Right Channel
2
LSB M SB 16 Clocks 16 Clocks
LSB
SDI, SDO
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Fig.8-5 Left-Justified Data Format 32Fs, 16bit Data
LRI, LRO BCKI, BCKO
M SB LSB M SB 16 Clocks 16 Clocks LSB Left Channel Right Channel
SDI, SDO
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Fig.8-6 Right-Justified Data Format 32Fs, 16bit Data
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4.3 Serial Audio Timing Table 10 Serial Audio Input Timing Parameters Parameter Symbol Test Condition
BCK Frequency * BCK Period * Low Pulse Width High Pulse Width BCK to LR Time * LR to BCK Time * Data Setup Time ** Data Hold Time ** fBCK tSIL tSIH tSLI tLSI tDS tDH Min 35 35 15 15 15 15
( VDD= VDDPWM=3.3V, Ta=25C ) Typ. Max Units
10 MHz ns ns ns ns ns
* It is regulations of the sampling converter interface. ** The terminal SDI selecting the sampling rate converter is regulations to BCKI. Exact to BCKO.
LR
tSIH tSIL tSLI tLSI
BCK
tDS tDH
SDI
Fig. 9 Serial Audio Input Timing ( VDD= VDDPWM=3.3V, Ta=25C ) Typ. Max Units
15 15 ns ns
Table 11 Serial Audio Output Timing Parameters Parameter Symbol Test Condition
BCK to LR Time Data Output Delay *** tSLO tDOD CL=25pF
Min -15 -
*** It is regulations to SDO, OUTRN1, OUTLN1 set to the serial audio output.
LR
tSLO
BCK
tDOD
SDO***
Fig.10 Serial Audio Output Timing
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NJU26060 Series
5. PWM Modulator
The NJU26060 Series provide the PWM modulator with two stereo (four channels) outputs. The PWM modulator employs eight-times over-sampling digital-filters, the fifth order modulators, and the modulation efficiency is 88%. The dynamic range is over 90dB. The PWM modulator provides the function of "noise suppression at silence period" and this function improves the S/N ratio up to 100dB. The PWM switching frequency is eight times of the sampling frequency. For example, 384kHz at Fs=48kHz, 352.8kHz at Fs=44.1kHz. The NJU26060 Series can directly drive the speakers with the power drivers because of the high modulation efficiency. After the reset the PWM modulator is standby mode. So the PWM modulator should be initialized by the firmware after the reset.
Table12 PWM Modulator Pin Assignment
Pin No. 23 22 3 2 29 28 17 24 25 26 27 21 20 19 18 Symbol VDDPWM VSSPWM PWM_DISb PWM_MUTEb PWM_ERRb PWMEN0 PWMEN1 OUTLP0 OUTLN0 OUTRP0 OUTRN0 OUTLP1 OUTLN1 OUTRP1 OUTRN1 Attribute PP GP I+ I+ I+ O O O O O O O O O O PWM Power Supply +3.3V PWM Power Supply GND PWM Block Standby request input pin (PWM_DISb =`0':Stand-BY) PWM Block Mute request input pin (PWM_MUTEb= `0':Mute) PWM block stop request input pin (PWM_ERRb='0': PWM stop) PWM0 enable output pin (PWMEN0='1': enable) PWM1 enable output pin (PWMEN1='1': enable) PWM0 L channel + output PWM0 L channel - output PWM0 R channel + output PWM0 R channel - output PWM1 L channel + output PWM1 L channel - output PWM1 R channel + output PWM1 R channel - output Description
Note:
I+: Input (Pull-up), O: Output, PP: PWM Power Supply, PG: PWM Power Supply GND
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The firmware or the external pins can select the PWM modulator functions in table13.
Table13 PWM Modulator Function
Description (Symbol) PWM Recognition signal (PWMEN0, PWMEN1) PWM Modulator stand by (PWM_DISb) Mute Function (PWM_MUTEb) Request PWM Error signal ( PWM_ERRb) Extend BPZ Output Function The terminal OUTLN1 is switched to selial audio output 0. ** The OUTRN1 is connected to serial audio output 1. ** Noise suppression function at silence period Short plus limitation Setting Pin Available Available * Available * Available * Not Available Not Available Not Available Not Available Not Available Firmware Available Available Available Available Available Available Available Available Available Default (Reset) Invalid Stand-By Mute Stop Invalid OUTLN1 OUTRN1 Effective Invalid
* The firmware can mask the external input for the each block. ** BPZ is bipolar zero. The BPZ is a clock waveform of duty50%. It changes automatically if 'BPZ output function' is set to the PWM1 block.
5.1 PWM Effective Signal / PWM Modulator Standby
The PWMEN0/1 output shows whether the PWM output is effective or not. The PWM modulator is standby mode after the power-on or the reset and the PWMEN0/1 pin becomes GND level. The firmware can activate the PWM modulator. The PWM_DISb pin and the firmware can make the PWM modulator standby.
PWM_DISbor PWM_DISb pin firmware setting PWMENx PWMENx pin
Sound output
GND level GND
Regular volume
PWM is clear PWM
Only the `Noise suppression function at silence period'.
BPZ BPZ
GND level GND
15ms @ Fs=48kHz 21.3ms @ Fs=48kHz 15ms@Fs=48kHz 21.3ms@Fs=48kHz 16.3ms @ Fs=44.1kHz 23.2ms @ Fs=44.1kHz 16.3ms@Fs=44.1kH 23.2ms@Fs=44.1kH
720/Fs 720/Fs
1024/Fs 1024/Fs
21.3ms @ Fs=48kHz 1365ms @ Fs=48kHz 5.33ms Fs=48kHz 21.3ms@Fs=48kHz 1365ms@Fs=48kHz 5.81ms @@Fs=44.1kHz 5.33ms@Fs=48kHz 23.2ms @ Fs=44.1kHz 1486ms @ Fs=44.1kHz 23.2ms@Fs=44.1kH 1486ms@Fs=44.1kH 5.81ms@Fs=44.1kH
1024/Fs 1024/Fs
65536/Fs 65536/Fs
256/Fs 256/Fs
Fig.11 Relation between `PWM Modulator Standby' and `PWMEN, PWM output'
(Fs=48kHz: CLK=24.576MHz, Fs=44.1kHz: CLK=22.5792MHz)
After releasing the standby mode, the PWM modulator sets PWMEN0/1 pin High level and outputs the PWM signal. After activating PWM modulator, the mute is released and the signal goes up to the maximum level. This procedure takes 1,024/Fs. This mute release procedure does not provide zero-cross function. By setting standby mode, the PWM modulator becomes the mute mode within 1,024/Fs.This mute procedure does not provide zero-cross function. If "noise suppression at silence period" mode becomes active, the clearance of the modulator is started. This procedure takes 65,536/Fs maximally. If "noise suppression at silence period" mode is not active, the clearance time is zero. After that, BPZ signal is outputted during some periods and the PWMEN0/1 signal becomes Low. Also the PWM signal output stops at the same time as PWMEN0/1=Low. The signal level of the PWM output becomes GND level.
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NJU26060 Series
5.2 Mute
The NJU26060 Series can mute the PWM modulator by setting PWM_MUTEb low or the firmware. The each L/R channel is muted or unmated respectively. The mute or un-mate is done at zero cross point. The step of the mute or the un-mute is 0.25dB/Fs. In case of very low input frequency, the mute or un-mute is not finished within 2048/Fs. In the above case, the mute or un-mute is done with 1/Fs step. So the mute or un-mute operates under time-out condition. And the time of the mute or un-mute is not fixed under time-out condition. If this time-out condition is not good for the system, the firmware can be designed to control the time of mute or un-mute.
5.3 Stop Function for the PWM Modulator
In case that the backend IC becomes abnormal condition, the firmware or PWM_EERb=Low can stop the PWM modulator fast. But the pop noise happens. To stop or release the PWM modulator function takes eight CLK clocks. To release the stop condition of the PWM modulator, PWM_STBYb should be High.
PWM_ERRb pin or PWM_ERRb firmware setting PWMENx pin PWMENx GND level GND
Sound output
Regular volume
326ns @ CLK=24.576MHz 326ns@CLK=24.576MHz 354ns @ CLK=22.5792MHz 354ns@CLK=22.5792MHz
CLK 8 clock CLK 8
Fig.12
Relation between PWM Reset and PWMEN, PWM Output
5.4 BPZ Output Extension (BPZ : Bipolar Zero)
In case that PWMEN0/1 is GND, the PWM output is GND to prevent the power-on pop noise. The firmware can generate BPZ before and PWMEN0x=High by BPZ Output extension. The fig.13 shows the relation among PWM_DISb, PWMENx, and the sound output. The BPZ is inserted before and after PWMENx=High. The PWM modulation should be active to keep PWM modulator output.
PWM_DISb PWM_DISb pin or firmware setting
PWMENx pin
PWMENx
Sound output
GND level GND
BPZ BPZ
Regular volume
PWM is clear BPZ PWM BPZ Only the `Noise suppression function at silence period'. 256/Fs 256/Fs
BPZ BPZ
GND level GND
15ms @ Fs=48kHz 15ms@Fs=48kHz 21.3ms@Fs=48kHz 21.3ms @ Fs=48kHz 16.3ms @ Fs=44.1kHz 23.2ms @ Fs=44.1kHz 16.3ms@Fs=44.1kH 23.2ms@Fs=44.1kH
720/Fs 720/Fs
1024/Fs 1024/Fs
21.3ms @ Fs=48kHz 1365ms @ Fs=48kHz 5.33ms @ Fs=48kHz 8.0ms @ Fs=48kHz 21.3ms@Fs=48kHz 1365ms@Fs=48kHz 5.33ms@Fs=48kHz @8.0ms@Fs=48kHz 23.2ms @ Fs=44.1kHz 1486ms @ Fs=44.1kHz 5.81ms @ Fs=44.1kHz 8.71ms Fs=44.1kHz 23.2ms@Fs=44.1kHz 1486ms@Fs=44.1kH 5.81ms@Fs=44.1kH 8.71ms@Fs=44.1kH
1024/Fs 1024/Fs 65536/Fs 65536/Fs
384/Fs 384/Fs
Fig.13
Relation between `BPZ Output Extension' and `PWMEN, PWM output'
(Fs=48kHz: CLK=24.576MHz, Fs=44.1kHz: CLK=22.5792MHz)
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5.5 Switching from the PWM output to the serial audio output In case that the BPZ output extension of PWM1 block is activated, the next two pins are assigned as follows: OUTLN1 : Serial audio output0 that is same as PWM0 signal OUTRN1: Serial audio output1 that is same as PWM1 signal These pins are PWM outputs after power-on.
5.6 Noise Suppression at Silence Period
The noise suppression function of the PWM modulator can suppress an internal idle noise of the modulator in no input signal. This noise suppression function is active in default. After the input of the PWM modulator becomes no signal, this function clear the internal PWM modulator within 65536/Fs and suppresses the internal noise. If the audio signal comes into the PWM modulator, the PWM modulator stops the noise suppression and generates the audio signal without any lack of audio signal. To activate the noise suppression function, the input signal should be complete no signal. The mute function of the PWM modulator can clear all input signal and the noise suppression becomes active. In case of the firmware mute, the input signal should be complete zero. Otherwise this function is not activated.
5.7 Short Plus Limitation
The PWM modulator generates the shortest 'Low' level pulse of 20nsec. The PWM modulator provides the four kinds of pulse width limitation by the firmware in fig.14. These pulse limitations do not include rising-time and falling-time of the pulse at the PWM output pin.
The minimum "L" level width restriction value CLK Frequency (Internal processing Fs)
Set level 0 (default) 1 2 3
22.5792MHz (Fs=44.1kHz) 0ns(no limit) 22.1ns 44.3ns 66.4ns
24.576MHz (Fs=48kHz) 0ns (no limit) 20.3ns 40.7ns 61.0ns
Table14 Shortest Pulse limitation
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5.8 PWM Modulator Characteristics Table15 PWM Modulator characteristics (CLK=24.576MHz(Fso=48kHz),LRI=48kHz,BCKI=3.072MHz, VDD=VDDPWM=3.3V,Ta=25)
Parameter THD+N (1kHz, 0dBFS) S/N ratio (1kHz, Noise decrease function as no-sound On, A-Weight) Dynamic range (1kHz, -60dBFS, A-Weight) Channel Separation (1kHz BPF) Min 90 85 90 Typ -85 100 90 100 Max -75 Unit dB dB dB dB
The characteristics in table15 are measured with the next circuits in fig.14. This circuit includes the second low-pass filters (cut-off frequency 50kHz). The Audio Precision measures the signal with the AES17 filter (20KHz LPF). The condition of this measurement: 1) The conversion ratio of the SRC is 1:1 (48kHz -> 48kHz). 2) The outputs of the SRC go to the output pins without any DSP processing. With this measurement condition, the power supply and the internal noise are added to the PWM output. The common mode noise is suppressed with the differential inputs. But the common mode noise is not suppressed with the single-end inputs. These characteristics have possibility to be degraded by the SRC. Because the sample rate converter is asynchronous, so some frequency degrades the characteristics.
Audio Precision SYS-2722
fc=50kHz 2nd order Active LPF fc=50kHz 2nd order Active LPF
OUTLP0 BCKI LRI SDI0 OUTLN0
Analyzer
S/N Ratio (A-weight) Dynamic Range (A-weight) THD+N Channel Separation (1kHz BPF)
NJU26060
DSP:Through SRC:On(Fso=48kHz) OUTRP0 OUTRN0
fc=50kHz 2nd order Active LPF fc=50kHz 2nd order Active LPF
20kHz LPF (AES17)
I2S Audio Signal (Fsi=48kHz)
Signal Generator
Fig.14 PWM Modulator Measuring circuit (OUTLP1/LN1/RP1/RN1A are also the same)
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6. Digital Interface Transemitor (DIT)
The NJU26060 series provides Digital Interface Transemitor. The DIT is compliant with AES3, IEC60958, S/PDIF and EIAJ CP1201 consumer specification. The DIT generates bi-phase signal that is CLK/512 frequency. The SDO generates bi-phase signal. The SDO is assigned as serial audio output in default. The firmware can change this output setting. The firmware can connect the GPIO[1] input to the SDO output. The SDO is hysteresis I/O pin with a pull-down resister, so the input level should be adjusted. The DIT channel status is shown in table 16. To connect a coaxial cable, the external buffer is recommended.
Table16 Channel Status Parameter
Channel Status Parameter CS0 CS1 CS2 CS3 CS4 CS5 CS6~7 CS8 CS9 CS10 CS11 CS12 CS13 CS14 CS15 CS16 ~19 CS20 ~23 CS24 CS25 CS26 CS27 CS28 CS29 Consumer/ Professional Data type Copyright Pre-emphasis Channel Mode 0: Consumer mode 0: Audio data, 1: Digital data 0: Protection, 1: No-Protection [CS3,CS4]=00: OFF [CS3,CS4]=10: ON 0: 2channel 00: mode 0 Prefer to standard book Category code Default [CS8:CS15]=0010000 Application of Japan to digital audio broadcasting reception. Source number Channel number Sampling Frequency 0000: no specification 0000: no specification [CS24:CS27]=0000 44.1kHz [CS24:CS27]=0100 48kHz [CS24:CS27]=1100 32kHz [CS28,CS29]=00 standard mode [CS28,CS29]=10 High precision mode Fixation Fixation Variable Variable Fixation/ Variable Fixation Variable Variable Variable Fixation Fixation Fixation Default 0 0 0 0 0 0 00 0 0 1 0 0 0 0 0 0000 0000 0 1 0 0 0 0
Clock Accuracy
Variable
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NJU26060 Series
7. Host Interface
The NJU26060 Series can be controlled via Serial Host Interface (SHI) using I2C bus. Data transfers are in 8 bit packets (1 byte) when using either format. Refer to Serial Host Interface Pin Description. (Table 4)
Table.17 Pin No. 5
4
Serial Host Interface Pin Description Symbol I2C bus Format SCL Serial Clock Serial Data Input SDA (Open Drain Input/Output)
Note : SDA pin (No.4) is a bi-directional open drain terminal. This pin requires a pull-up resister.
7.1 I2C bus Interface
I2C bus interface transfers data to the SDA pin and clocks data to the SCL pin. SDA pin is a bi-directional open drain and requires a pull-up resister. When the NJU26060 Series is configured for I2C bus communication during the Reset initialization sequence, I2C bus interface transfers data to the SDA pin and clocks data to the SCL pin. An address can be arbitrarily set up by the seven-bit SLAVE address of the serial host interface. (Table 5)
Table.17
bit 7 bit 6 bit 5
Serial Host Interface Pin Description
bit 4 bit 3 bit 2 bit 1 bit0 R/W
Default (Reset): 0b0011100 The setting is free in the firmware.
Start bit
Slave Address ( 7bit )
R/W bit
ACK
Note : The serial host interface supports "Standard-Mode (100kbps)" and "Fast-Mode (400kbps)" I2C bus data transfer.
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Table 19 I2C bus Interface Timing Parameters
Parameter SCL Clock Frequency Start Condition Hold Time SCL "Low" Duration SCL "High" Duration Start Condition Setup Time *1 Data Hole Time Data Setup Time Rising Time Falling Time Stop Condition Setup Time *2 Bus Release Time Symbol fSCL tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tR tF tSU:STO tBUF Min 0 0.6 1.3 0.6 0.6 0 250 0.6 1.3
( VDD=3.3V, fOSC=24.576MHz, Ta=25C )
Max 400 0.9 1000 300 Units kHz s s s s s ns ns ns s s
SDA tR tF
tBUF
tHD:STA
SCL
tHD:STA t LOW P S
tHD:DAT
tHIGH
tSU:DAT Sr
tSU:STA
tSU:STO P
Fig. 15 I2C bus Timing
Note : *1 tHD:DAT: Keep data 100ns hold time to avoid indefinite state by SCL falling edge. *2 This item shows the interface specification. The interval of a continuous command is specified separately.
8General-purpose in/out pin
The NJU26060 Series has general-purpose in/out pin. GPIO0 pin includes with TEST mode and limits for starting up. Table 20 General-purpose in/out pin and pin disposal
Pin No. 40 39 38 37
Symbol
GPIO0 (Pull-down I/O) GPIO1 (Pull-down I/O) GPIO2 (Pull-up I/O) GPIO3 (Pull-up I/O)
Description
Starts with "Low". It depends on the firmware after it starts. It depends on the firmware. It depends on the firmware. It depends on the firmware.
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NJU26060 Series
9Package
SSOP44, Pb-Free
BASE OF MOLDING
UNIT: mm
[CAUTION] The specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. The application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights.
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